Field of the Invention
The invention is directed to a data serialization circuit and more particularly, to the data serialization circuit with lower jitter re-sampling scheme.
Description of Related Art
In conventional art, a plurality of clock trees are necessary for an integrated circuit (IC). The clock trees are used to provide a plurality of clock signals to a core circuit of the IC. The core circuit can sample data by using the clock signals. Under a noisy power and/or ground environment, jitter of each of the clock signals increases according to number of delay stages of the clock tree for generating each of the clock signals. As a result, size of a window of an eye diagram corresponding to data sampled by the clock signal with higher jitter is reduced. Quality of the sampled data declines correspondingly.